Journal of Advanced Materials in Engineering (Esteghlal)

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A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of functional units and their repetitive use. Digital signal processing applications often involve high-speed sequential data. Bit-serial processing in particular can result in efficient communications, both within and between VLSI chips because of the reduced number of interconnections required. Serial input multipliers have received considerable attention, particularly for hardwired VLSI algorithms used in signal processing application, due to their minimal chip area required for interconnections. Bit-serial architectures are often used in parallel systems with high connectivity to reduce the wiring down to a reasonable level. The conventional add-shift technique for multiplication, which uses a minimum number of gates, is inexpensive to implement, but too slow to achieve the desired result. Iterative array multipliers are needed to satisfy the high speed requirement of systems. With the advantage of high scale integration, the hardware is not regarded as a major obstacle in implementation.

Keywords: : Systolic arrays, Serial multiplier, Systolic multiplier, FPGA and HDL.

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